A technology for generating a simulation method and performing simulation is proposed by the applicant of the present invention, wherein the simulation method comprises the steps of receiving a source file, composed of a behavior level description, for behavioral synthesis with the behavior level description (algorithm description) as the hardware description; creating a finite state machine/data path model description, a variable/register/state position correspondence table, and a behavior level description source line/state position correspondence table, as a simulation model; and performing clock-level simulation (for example, see Patent Document 1).
Patent Document 1 discloses a configuration in which, when a state transition occurs, the current state position is obtained, the source line corresponding to the state position is obtained from the line information table, and the source line is highlighted (or displayed in reverse video) on the GUI (Graphical User Interface) such as an execution display window as shown in FIG. 18 for letting the user identify the current execution position on the behavior level description. For how to create a finite state machine/data path model description and a behavior level description source line/state position correspondence table from a behavior level description, also see the description in Patent Document 2, proposed by the applicant of the present invention, that is given below.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-109788A (FIG. 9, FIG. 11)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2003-67438A (FIG. 2, FIG. 5)
As described in Patent Documents 1 and 2, a method for allowing the user to recognize the correspondence between the simulation execution states and the behavior level description source during the simulation of the hardware description including a behavior level description is efficient, for example, in a circuit design process.
According to the method described in Patent Document 1, the correspondence between the simulation execution states and the behavior level description source lines in the simulation model of a finite state machine structure is based on state transition units, for example, state 1 corresponds to the third line of source File1.c, state 2 is to the fourth line of source file File2.c, and state 3 is to the fourth line of source file File 3.c (see FIG. 9 in Patent Document 1).
A simulation model sometimes includes a conditional branch in a state entered by a transition (for example, see if statement in FIG. 18). And, it is known that, in a hardware description, there is a relatively high possibility that a bug lurks in a conditional branch.
In consideration of the fact described above, the inventor of the present invention has found that the correspondence between the simulation execution states and the behavior level description source lines should be based, not on a state transition, but on a conditional branch statement whose granularity is finer than that of the state transition, to provide the user with more detailed information to increase debugging accuracy and circuit design efficiency.
The inventor of the present invention has also found that the method described in above-described Patent Document 1 for managing the correspondence between the simulation execution states and the behavior level description source lines on a state transition basis can be improved to implement a function that establishes the correspondence between conditional branch statements included in a behavior level description and the simulation execution states.